1. Technical Field of the Invention
The present invention relates to a method for producing capacitor elements, and a capacitor element. In particular, the invention is directed at a method for producing capacitor elements, which enables improved operating reliability of capacitor elements.
2. Description of the Related Arts
Recently, in order to increase the capacitance of a capacitor element that constitutes a semiconductor device, for example, a DRAM (Dynamic Random Access Memory), a technology (HSG technology), which forms an HSG (Hemispherical Grain) in a lower electrode of a capacitor element, has been frequently employed.
In the HSG technology, thermal processing is applied to an amorphous silicon layer in a vacuum state to migrate silicon atoms, and an HSG is formed on the film surface, whereby the surface area of the lower electrode is increased, resulting in an increase in the capacitance of a capacitor element.
In the HSG technology, there are mainly two types of method, one of which is a blanket HSG method, and the other of which is a selection HSG method.
In the blanket HSG method, an amorphous silicon layer is formed in an LP-CVD (Low Pressure Chemical Vapor Deposition) furnace, thereby forming an HSG. In detail, the pressure in the LP-CVD furnace is set to, for example, 0.2 Torr or so, and the temperature is set to, for example, a transition temperature or so between amorphous and crystal, wherein a silane gas or a disilane gas is introduced into the furnace to form a silicon layer. After the silicon layer is formed, the supply of silane gas is stopped, wherein annealing is carried out for several minutes with a vacuum inside the furnace. And, silicon atoms are migrated to form an HSG on the film surface.
On the other hand, in the selection HSG method, an amorphous silicon layer is formed in advance and patterning is applied thereto. Natural oxide films and organic substances existing on the surface of the film are removed to clean the surface. Thereafter, an HSG is formed on the surface of an amorphous silicon layer, using an LP-CVD furnace, etc. In detail, the pressure inside the LP-CVD furnace is set to, for example, 1mTorr or so, and a silane gas is irradiated on the clean surface of the amorphous silicon layer, whereby micro crystals which become the growth nuclei of HSG are formed on the surface of the amorphous silicon layer. After that, the supply of silane gas is stopped, and the amorphous silicon layer containing micro crystals is annealed in a state where the pressure inside the furnace is kept on 1xc3x9710xe2x88x927 Torr or less, whereby silicon atoms are migrated to form an HSG on the film surface.
Also, even though either technology of the abovementioned blanket HSG method or the selection HSG method is employed, the HSG just after being formed includes almost no impurities. That is, almost no carrier is included in the just formed HSGs. Where almost no carrier exists in an electrode of a capacitor element, the capacitance is lowered due to depletion of the electrode.
One of the methods for diffusing impurities in the HSG is a method of injecting impurities from outside an HSG. For example, after an HSG is formed on the surface of a silicon layer, thermal processing is carried out at 700xc2x0 C. in the atmosphere of POC13 (phosphorus oxytrichloride), using an LP-CVD furnace, etc. As described above, by thermally processing in the atmosphere of POC13, impurities can be sufficiently diffused in the HSG. But, the POC13 forms a smooth phosphorus glass film on the HSG surface by reaction with silicon contained in the HSG. The phosphorus glass film fills up clearance between the HSGs, resulting in a lowering of the surface area of the lower electrode. Therefore, the phosphorus glass film on the HSG surface must be removed by using fluoric acid, etc. However, since the phosphorus glass film is formed by a chemical reaction with silicon, there arises a problem by which the size of the HSG is made very small or some HSGs are omitted by removing the phosphorus glass film.
In addition the above description, technologies for diffusing impurities in HSGs are disclosed by Japanese Laid-Open Patent Publication Nos. 70249 of 1998 and 303368 of 1998.
In the technology disclosed in Japanese Laid-Open Patent Publication No. 70249 of 1998, impurities are injected into the HSGs by using an ion injection method after HSGs are formed on a silicon layer surface.
In the technology disclosed in Japanese Laid-Open Patent Publication No. 303368 of 1998, after HSGs are formed on a silicon layer surface, natural oxide films and contaminated substances on the surface of the HSGs are removed by using a wet type detergent such as a hydrogen fluoride acid solution and BOE (Buffer oxide etching solution), etc. Thereafter, impurities are diffused in the HSGs, using an LP-CVD apparatus and RTP (Rapid Thermal Processing) apparatus. In detail, in the case where an LP-CVD apparatus is used, thermal processing is carried out at 650 through 850xc2x0 C. in an atmosphere of phosphine (PH3) to cause phosphorus to diffuse in the HSGS. On the other hand, in the case where the RTP apparatus is used, thermal processing is carried out at 550 through 900xc2x0 C. in an atmosphere of phosphine to cause phosphorus to diffuse in the HSGS. In detail, in the LP-CVD apparatus, thermal processing is carried out at 700xc2x0 C. for three hours and, in the RTP apparatus, thermal processing is carried out at 800xc2x0 C. for 300 seconds.
In Japanese Laid-Open Patent Publication No. 303368 of 1998, such a technology has been disclosed, in which phosphine exited by plasma discharge is irradiated on HSGs for annealing in order to diffuse impurities in the HSGs.
However, the technologies disclosed in Japanese Laid-Open Patent Publication Nos. 70249 of 1998 and 303368 of 1998 described above still have the-following problems.
In the technology disclosed in Japanese Laid-Open Patent Publication No. 70249 of 1998, it is difficult to uniformly irradiate ions on the upper and lower parts of a cylinder type lower electrode, in particular, on a lower electrode having a high aspect ratio. Besides, if the energy for injection of ions is increased to dope sufficient impurities on the lower part of the lower electrode, there may arise such a problem by which the HSGs may collapse or be missed.
In Japanese Laid-Open Patent Publication No. 303368 of 1998, it has been found that a hold defect (an error caused when an electric charge cannot be maintained sufficiently long) frequently occur when making practical operations. Based on the results of analysis made by the present inventors, etc., the hold defect arises when water marks and natural oxide films exist in a minute area of the lower electrode having HSGs, and impurities are not sufficiently diffused in the lower electrode (HSG). Such water marks and natural oxide films remain when cleaning the HSG surface with a wet type detergent or may be formed in a drying process after cleaning. This is liable to occur after the HSGs are formed, and it is considered that it results from the shape thereof.
Also, recently, there are cases where a semiconductor device is constructed by the mixed of mounting DRAMs and logic circuits on the same chip. In a logic circuit production process, since a salicide (self-align silicide) process resides in a process-for producing logic circuits, the thermal allowance (amount of thermal load applied) is decreased in the process for producing DRAMs. In detail, in the case where a normal furnace is used, the thermal processing temperature must be 600xc2x0 C. or less. And in the case where the RTP apparatus is used, processing at 800xc2x0 C. or so for several minutes in total may be allowable.
In the technology disclosed by Japanese Laid-Open Patent Publication No. 303368 of 1998, where an LP-CVD apparatus is used, thermal processing is carried out at 700xc2x0 C. for three hours. Therefore, the temperature exceeds the abovementioned thermal allowance in the process of formation of a lower electrode. On the other hand, where an RTP apparatus is used, thermal processing is carried out at 800xc2x0 C. for 300 seconds, wherein the abovementioned thermal allowance is used in only the process of formation of a lower electrode. Also, in the case of thermal processing at 600xc2x0 C. or less, sufficient impurities to suppress the depletion of the electrode cannot be diffused in the HSGs even though thermal processing is carried out for six hours. That is, it is found that this is not realistic.
In the technology disclosed by Japanese Laid-Open Patent Publication No. 303368 of 1998, in which plasma discharge is used, it is possible to diffuse a sufficient amount of phosphorus in the HSGs by thermal processing at 700xc2x0 C. for 300 seconds. However, where a device (DRAM) was actually produced, it was observed that an increase in leak currents, etc., occurs at the gate insulation layer of a transistor connected to the lower electrode of a capacitor. In addition, in the plasma discharge, another problem occurs, by which phosphorus is likely to be deposited on the inner wall of a furnace, and generation of particles is increased.
Still further, as disclosed in Japanese Laid-Open Patent Publication No. 303368 of 1998, in order to prevent impurities from being re-diffused into the HSGs where thermal processing is carried out at a high temperature such as 700xc2x0 C. or 800xc2x0 C., a wafer is taken out of the furnace with the temperature reduced to 600xc2x0 C. or so. Therefore, it takes much time to raise and lower the temperature, resulting in still another problem which is that of lowered production efficiency in the production of capacitor elements.
Therefore, it is an object of the invention to provide a method for producing capacitor elements, by which production efficiency can be improved. Also, it is another object of the invention to provide a capacitor element that is highly reliable in operation. Further, it is still another object of the invention to provide a method for producing capacitor elements at a low temperature, which is capable of reducing depletion of an electrode, that constitutes a capacitor element.
In order to achieve the abovementioned objects, a method for producing capacitor elements according to a first aspect of the invention is a method for producing capacitor elements constructed of a lower electrode, a dielectric body layer and an upper electrode, which are formed on a semiconductor substrate, comprising a first silicon layer forming step for forming a first amorphous silicon layer at an appointed area on the semiconductor substrate, a lower electrode surface rinsing step for rinsing the surface of the first silicon layer, a nucleus forming step for selectively forming a second amorphous silicon layer including microcrystal on the surface of the first silicon layer, an HSG forming step for growing HSGs (hemispherical Grains) using microcrystal included in the second silicon layer as a nucleus by annealing the first and second silicon layer at a low pressure or in the atmosphere of an inactive gas, and forming HSGs on the surface of the first silicon layer, an impurity diffusing step for forming a lower electrode by annealing while the HSGs are being exposed to a source gas including impurities and thermally diffusing the impurities in the HSGs, a dielectric body layer forming step for forming a dielectric body layer on the first silicon layer having the HSGs on the surface thereof, and an upper electrode forming step for forming an upper electrode on the dielectric body layer, wherein the partial pressure of oxygen and water is maintained at 1xc3x9710xe2x88x926 Torr or less at least between the HSG forming step and the impurity diffusing step.
With the invention, it is possible to prevent water marks and natural oxide films, etc., from being formed on the surface of HSGS. Therefore, a sufficient amount of impurities can be diffused in the HSGs even at a lower temperature like, for example, 550xc2x0 C.
The nucleus forming step, the HSG forming step, and the impurity diffusing step may be carried out in the same reaction chamber of an LPCVD apparatus (low pressure chemical vapor deposition apparatus).
If so, it is possible to easily maintain the partial pressure of oxygen and water in the reaction chamber at 1xc3x9710xe2x88x926 Torr or less from the nucleus forming step to the impurity diffusing step.
In the nucleus forming step and the HSG forming step, the partial pressure of a remaining PH3 gas in the reaction chamber may be set to 1xc3x9710xe2x88x924 Torr or less.
If so, it is possible to prevent HSG growth from being suppressed.
After the impurity diffusing step, a step for reducing a remaining PH3 gas in the reaction chamber may be further provided, wherein after the semiconductor substrate is taken out from the reaction chamber, a gas containing silane or disilane is introduced into the reaction chamber.
Thereby, it is possible to prevent the HSG growth from being suppressed in the next HSG forming step.
A step, in which the minimum temperature on the inner wall of the reaction chamber is kept at 60xc2x0 C. or more, a PH3 gas adsorbed at a low temperature portion in the reaction chamber is removed, and the remaining PH3 in the corresponding reaction chamber is reduced, may be further provided.
Thereby, it is possible to prevent HSG growth from being suppressed in the next HSG forming step.
Still another step may be provided, where a series of actions are repeated an appointed number of times., in which after the impurity diffusing step, an inactive gas is introduced into the reaction chamber after the semiconductor substrate is taken out from the reaction chamber, the pressure of the reaction chamber is increased and is kept for an appointed period of time, and subsequently the pressure is reduced, the low temperature portion in the reaction chamber is heated to allow the progression of the removal of PH3 gas adsorbed on the low temperature portion in the reaction chamber, and the remaining PH3 gas in the reaction chamber is reduced.
Thereby, it is possible to prevent HSG growth from being suppressed in the next HSG forming step.
Too much time is needed to diffuse impurities at a temperature lower than 550xc2x0 C. in the impurity diffusing step. Also, since the surface of the HSGs is not oxidized, separation of impurities will be greater than absorption thereof at a temperature exceeding 600xc2x0 C., wherein there are cases where the shape of the HSGs will collapse. Therefore, the impurity diffusing step is carried out at a temperature from 550 through 600xc2x0 C.
The annealing temperature in the HSG forming step may be substantially equal to that in the impurity diffusing step.
Thus, since it is not necessary to raise or lower the temperature in the reaction chamber, the time required to form capacitor elements can be accordingly reduced, and production efficiency can be improved. Also, since it is possible to prevent particles from being generated in line with raising and lowering of the temperature, highly reliable capacitor elements can be formed.
An etching step for etching the surface area of the HSGs may be further provided before the dielectric body layer forming step. Thereby, the reliability of capacitor elements thus formed can be improved. The etching may be performed in a depth from 1 nm through 5 nm from the surface of the HSGs.
A step for lowering the concentration of impurities on the surface of the HSGs by annealing with reduced pressure may be further provided after the impurity diffusing step. Thereby, the reliability of the capacitor elements thus formed can be improved.
The concentration of impurities on the surface of the HSGs before the dielectric body layer forming step may be set to a value lower than 3xc3x971020 atoms/cm3. The impurities contained in the source gas may be PH3.
The first silicon forming step may be also provided, before the nucleus forming step, with a step for forming the first silicon layer on the inner wall of a recess held by an insulation layer formed on the semiconductor substrate and for removing at least a part of the insulation layer so that the first silicon layer formed on the inner wall of the recess protrudes from the corresponding recess. Thereby, the formed area of HSGs can be widened to increase the capacitance of the capacitor elements.
A method for producing capacitor elements according to a second aspect of the invention is a method for producing capacitor elements constructed of a lower electrode, a dielectric body layer, and an upper electrode, which are formed on a semiconductor substrate, comprises a first silicon layer forming step for forming a first amorphous silicon layer on the entire surface including the inner wall of a recess on an insulation layer having the recess at an appointed part, a lower electrode rinsing step for rinsing and cleaning the surface of the first silicon layer, a nucleus forming step for forming a second amorphous silicon layer including microcrystal on the surface of the first silicon layer, an HSG forming step for growing HSGs (hemispherical Grains) using microcrystal included in the second silicon layer as a nucleus by annealing the first and second silicon layer at a low pressure or in the atmosphere of an inactive gas, and forming HSGs on the surface of the first silicon layer, an impurity diffusing step for forming a lower electrode by annealing while the HSGs are being exposed to a source gas including impurities and thermally diffusing the impurities in the HSGs, a lower electrode forming step for forming a lower electrode in the recess by etching back the first silicon layer having the HSGs on the surface thereof, a dielectric body layer forming step for forming a dielectric body layer on the surface of the lower electrode, and an upper electrode forming step for forming an upper electrode on the surface of the dielectric body layer, wherein the partial pressure of oxygen and water is maintained at 1xc3x9710xe2x88x926 Torr or less at least between the HSG forming step and the impurity diffusing step. According to the invention, it is possible to prevent water marks and natural oxide films, etc., from being formed on the surface of HSGs. Therefore, a sufficient amount of impurities can be diffused in the HSGs even at a lower temperature such as, for example, 550xc2x0 C.
The nucleus forming step, the HSG forming step, and the impurity diffusing step may be carried out in the same reaction chamber of an LPCVD apparatus (low pressure chemical vapor deposition apparatus).
If so, it is possible to easily maintain the partial pressure of oxygen and water in the reaction chamber at 1xc3x9710xe2x88x926 Torr or less from the nucleus forming step to the impurity diffusing step.
In the nucleus forming step and the HSG forming step, the partial pressure of a remaining PH3 gas in the reaction chamber may be set to 1xc3x9710xe2x88x924 Torr or less. If so, it is possible to prevent the HSG growth from being suppressed.
After the impurity diffusing step, a step for lowering a remaining PH3 gas in the reaction chamber may be further provided, wherein after the semiconductor substrate is taken out from the reaction chamber, a gas containing silane or disilane is introduced into the reaction chamber. Thereby, it is possible to prevent HSG growth from being suppressed in the next HSG forming step.
A step, in which the minimum temperature on the inner wall of the reaction chamber is kept at 60xc2x0 C. or more, the PH3 gas adsorbed at a low temperature portion in the reaction chamber is removed, and the remaining PH3 in the corresponding reaction chamber is lowered, may-be further provided. Thereby, it is possible to prevent the HSG growth from being suppressed in the next HSG forming step. Still another step may be provided, where a series of actions are repeated an appointed number of times, in which after the impurity diffusing step, an inactive gas is introduced into the reaction chamber after the semiconductor substrate is taken out from the reaction chamber, the pressure of the reaction chamber is increased and is kept for an appointed period of time, and subsequently the pressure is reduced, the low temperature portion in the reaction chamber is heated to allow the progression of removal of PH3 gas adsorbed on the low temperature portion in the reaction chamber, and the remaining PH3 gas in the reaction chamber is reduced. Thereby, it is possible to prevent the HSG growth from being suppressed in the next HSG forming step.
Too much time is needed to diffuse impurities at a temperature lower than 550xc2x0 C. in the impurity diffusing step. Also, since the surface of the HSGs is not oxidized, separation of impurities will be greater than absorption thereof at a temperature exceeding 600xc2x0 C., wherein there are cases where the shape of HSGs will collapse. Therefore, the impurity diffusing step is carried out at a temperature from 550 through 600xc2x0 C.
The annealing temperature in the HSG forming step may be substantially equal to that in the impurity diffusing step. Thus, since it is not necessary to raise or lower the temperature in the reaction chamber, the time required to form capacitor elements can be accordingly reduced, and production efficiency can be improved. Also, since it is possible to prevent particles from being generated in line with the raising and lowering of the temperature, highly reliable capacitor elements can be formed.
An etching step for etching the surface area of the HSGs may be further provided before the dielectric body layer forming step. Thereby, the reliability of capacitor elements thus formed can be improved. The etching may be performed in a depth from 1 nm through 5 nm from the surface of the HSGs.
A step for lowering the concentration of impurities on the surface of the HSGs by annealing with reduced pressure may be further provided after the impurity diffusing step. Thereby, the reliability of the capacitor elements thus formed can be improved.
The concentration of impurities on the surface of the HSGs before the dielectric body layer forming step may be set to a value lower than 3xc3x971020 atoms/cm3. The impurities contained in the source gas may be PH3.
A step for removing at least a part of the insulation layer so that the lower electrode in the recess protrudes from the insulation layer may be also provided before the dielectric body layer forming step. Thereby, the area in which a dielectric body layer is formed is widened to accordingly increase the capacitance of capacitor elements.
Still further, a step for forming a protection material, which protects the inside of the recess when etching back in the corresponding lower electrode forming step, on the first silicon layer having the HSGs may be provided before the lower electrode forming step.
A method for producing capacitor elements according to a third aspect of the invention is a method for producing capacitor elements constructed of a lower electrode, a dielectric body layer, and an upper electrode, which are formed on a semiconductor substrate, comprises a first silicon layer forming step for forming a first amorphous silicon layer on the entire surface including the inner wall of a recess on an insulation layer having the recess at an appointed part, a nucleus forming step for forming a second amorphous silicon layer including microcrystal on the surface of the first silicon layer, an HSG forming step for growing HSGs (hemispherical Grains) using microcrystal included in the second silicon layer as a nucleus by annealing the first and second silicon layer at a low pressure or in the atmosphere of an inactive gas, and forming HSGs on the surface of the first silicon layer, an impurity diffusing step for forming a lower electrode by annealing while the HSGs are being exposed to a source gas including impurities and thermally diffusing the impurities in the HSGS, a lower electrode forming step for forming a lower electrode in the recess by etching back the first silicon layer having the HSGs on the surface thereof, a dielectric body layer forming step for forming a dielectric body layer on the surface of the lower electrode, and an upper electrode forming step for forming an upper electrode on the surface of the dielectric body layer, wherein the partial pressure of oxygen and water is maintained at 1xc3x9710xe2x88x926 Torr or less at least between the HSG forming step and the impurity diffusing step. According to the invention, it is possible to prevent water marks and natural oxide films, etc., from being formed on the surface of HSGs. Therefore, a sufficient amount of impurities can be diffused in the HSGs even at a lower temperature such as, for example, 550xc2x0 C.
The first silicon layer forming step, the nucleus forming step, the HSG forming step, and the impurity diffusing step may be carried out in the same reaction chamber of an LPCVD apparatus (low pressure chemical vapor deposition apparatus).
If so, it is possible to easily maintain the partial pressure of oxygen and water in the reaction chamber at 1xc3x9710xe2x88x926 Torr or less from the nucleus forming step to the impurity diffusing step.
In the nucleus forming step and the HSG forming step, the partial pressure of a remaining PH3 gas in the reaction chamber may be set to 1xc3x9710xe2x88x924 Torr or less. If so, it is possible to prevent the HSG growth from being suppressed.
After the impurity diffusing step, a step for lowering a remaining PH3 gas in the reaction chamber may be further provided, wherein after the semiconductor substrate is taken out from the reaction chamber, a gas containing silane or disilane is introduced into the reaction chamber. Thereby, it is possible to prevent HSG growth from being suppressed in the next HSG forming step.
A step may be further provided, in which the minimum temperature on the inner wall of the reaction chamber is kept at 60xc2x0 C. or more, the PH3 gas adsorbed at a low temperature portion in the reaction chamber is degased, and the remaining PH3 in the corresponding reaction chamber is lowered. Thereby, it is possible to prevent the HSG growth from being suppressed in the next HSG forming step. Still another step may be provided, where a series of actions are repeated an appointed number of times, in which after the impurity diffusing step, an inactive gas is introduced into the reaction chamber after the semiconductor substrate is taken out from the reaction chamber, the pressure of the reaction chamber is increased and is kept for an appointed period of time, and subsequently the pressure is reduced, the low temperature portion in the reaction chamber is heated to allow the progression of removal of PH3 gas adsorbed on the low temperature portion in the reaction chamber, and the remaining PH3 gas in the reaction chamber is reduced. Thereby, it is possible to prevent the HSG growth from being suppressed in the next HSG forming step.
Too much time is needed to diffuse impurities at a lower temperature than 550xc2x0 C. in the impurity diffusing step. Also, since the surface of HSGs is not oxidized, separation of impurities will be greater than absorption thereof at a temperature exceeding 600xc2x0 C., wherein there are cases where the shape of HSGs will collapse. Therefore, the impurity diffusing step is carried out at a temperature from 550 through 600xc2x0 C.
The annealing temperature in the HSG forming step may be substantially equal to that in the impurity diffusing step.
Thus, since it is not necessary to raise or lower the temperature in the reaction chamber, the time required to form capacitor elements can be accordingly reduced, and production efficiency can be improved. Also, since it is possible to prevent particles from being generated in line with raising and lowering of the temperature, highly reliable capacitor elements can be formed.
An etching step for etching the surface area of the HSGs may be further provided before the dielectric body layer forming step.
Thereby, the reliability of capacitor elements thus formed can be improved.
The etching may be performed to a depth from 1 nm through 5 nm from the surface of the HSGs.
A step for lowering the concentration of impurities on the surface of the HSGs by annealing with reduced pressure may be further provided after the impurity diffusing step.
Thereby, the reliability of the capacitor elements thus formed can be improved.
The concentration of impurities on the surface of the HSGs before the dielectric body layer forming step may be set to a value lower than 3xc3x971020 atoms/cm3.
The impurities contained in the source gas may be PH3.
A step for removing at least a part of the insulation layer so that the lower electrode in the recess protrudes from the insulation layer may be also provided before the dielectric body layer forming step.
Thereby, the area in which a dielectric body layer is formed is widened to accordingly increase the capacitance of capacitor elements.
Still further, a step for forming a protection material, which protects the inside of the recess when etching back in the corresponding lower electrode forming step, on the first silicon layer having the HSGs may be provided before the lower electrode forming step.
A capacitor element according to a fourth aspect of the invention comprises a first electrode formed on a substrate and having, on the surface thereof, HSGs whose concentration of impurities on the surface area is lower than 3xc3x971020 atoms/cm3, a capacitance insulation layer formed on the first electrode, and a second electrode formed on the interlayered insulation layer.
The HSGs may include impurities, whose concentration is higher than 8xc3x971019 atoms/cm3 but lower than 3xc3x971020 atoms/cm3, on the surface area.
The HSGs may include impurities, whose concentration is higher than 8xc3x971019 atoms/cm3 but lower than 3xc3x971020 atoms/cm3, in a depth of 10 nm from the surface.
As has been made clear on the basis of the abovementioned description, with the invention, impurities sufficient to prevent depletion of electrodes can be diffused in the HSGs at a low temperature, and operation reliability of the capacitance elements can be improved. Still further, since a low temperature process is applied, it is possible to shorten the time required to raise and lower the furnace temperature, and production efficiency of semiconductor devices can be improved.